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/*************************************************************************** |
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* * |
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* Copyright (C) 2008 Andreas Persson * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
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* the Free Software Foundation; either version 2 of the License, or * |
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* (at your option) any later version. * |
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* * |
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* This program is distributed in the hope that it will be useful, * |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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* GNU General Public License for more details. * |
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* * |
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* You should have received a copy of the GNU General Public License * |
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* along with this program; if not, write to the Free Software * |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * |
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* MA 02110-1301 USA * |
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***************************************************************************/ |
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#ifndef LSATOMIC_H |
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#define LSATOMIC_H |
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/* |
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* Implementation of a small subset of the C++0x atomic operations |
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* (cstdatomic). |
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* |
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* The supported operations are: |
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* |
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* - fences (acquire, release and full) |
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* |
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* - load and store of atomic<int> with relaxed, acquire/release or |
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* seq_cst memory ordering |
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* |
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* The supported architectures are x86 and powerpc. |
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*/ |
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namespace LinuxSampler { |
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enum memory_order { |
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memory_order_relaxed, memory_order_acquire, |
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memory_order_release, memory_order_seq_cst |
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}; |
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inline void atomic_thread_fence(memory_order order) { |
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switch (order) { |
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case memory_order_relaxed: |
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break; |
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case memory_order_acquire: |
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case memory_order_release: |
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#ifdef _ARCH_PPC64 |
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asm volatile("lwsync" : : : "memory"); |
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#elif defined(_ARCH_PPC) |
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asm volatile("sync" : : : "memory"); |
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#else |
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asm volatile("" : : : "memory"); |
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#endif |
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break; |
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case memory_order_seq_cst: |
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#ifdef _ARCH_PPC |
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asm volatile("sync" : : : "memory"); |
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#elif defined(__i386__) |
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asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
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#elif defined(__x86_64__) |
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asm volatile("mfence" : : : "memory"); |
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#else |
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asm volatile("" : : : "memory"); |
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#endif |
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break; |
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} |
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} |
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template<typename T> class atomic { |
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public: |
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atomic() { } |
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atomic(T m) : f(m) { } |
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T load(memory_order order = memory_order_seq_cst) const volatile { |
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T m; |
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switch (order) { |
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case memory_order_relaxed: |
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m = f; |
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break; |
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case memory_order_seq_cst: |
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case memory_order_release: // (invalid) |
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atomic_thread_fence(memory_order_seq_cst); |
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// fall-through |
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case memory_order_acquire: |
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#ifdef _ARCH_PPC |
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// PPC load-acquire: artificial dependency + isync |
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asm volatile( |
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#ifdef _ARCH_PPC64 |
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"ld %0,%1\n\t" |
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#else |
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"lwz%U1%X1 %0,%1\n\t" |
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#endif |
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"cmpw %0,%0\n\t" |
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"bne- 1f\n\t" |
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"1: isync" |
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: "=r" (m) |
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: "m" (f) |
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: "memory", "cc"); |
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#else |
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m = f; |
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asm volatile("" : : : "memory"); |
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#endif |
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break; |
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} |
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return m; |
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} |
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void store(T m, memory_order order = memory_order_seq_cst) volatile { |
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switch (order) { |
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case memory_order_relaxed: |
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f = m; |
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break; |
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case memory_order_release: |
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atomic_thread_fence(memory_order_release); |
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f = m; |
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asm volatile("" : : : "memory"); |
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break; |
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case memory_order_seq_cst: |
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case memory_order_acquire: // (invalid) |
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atomic_thread_fence(memory_order_release); |
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f = m; |
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atomic_thread_fence(memory_order_seq_cst); |
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break; |
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} |
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} |
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private: |
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T f; |
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}; |
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} |
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#endif |