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/*************************************************************************** |
/*************************************************************************** |
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* * |
* * |
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* Copyright (C) 2008-2012 Andreas Persson * |
* Copyright (C) 2008-2013 Andreas Persson * |
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* * |
* * |
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* This program is free software; you can redistribute it and/or modify * |
* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
* it under the terms of the GNU General Public License as published by * |
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* - load and store of atomic<int> with relaxed, acquire/release or |
* - load and store of atomic<int> with relaxed, acquire/release or |
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* seq_cst memory ordering |
* seq_cst memory ordering |
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* |
* |
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* The supported architectures are x86 and powerpc. |
* The supported architectures are x86, powerpc and ARMv7. |
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*/ |
*/ |
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asm volatile("lwsync" : : : "memory"); |
asm volatile("lwsync" : : : "memory"); |
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#elif defined(_ARCH_PPC) |
#elif defined(_ARCH_PPC) |
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asm volatile("sync" : : : "memory"); |
asm volatile("sync" : : : "memory"); |
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#elif defined(__ARM_ARCH_7A__) |
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asm volatile("dmb" : : : "memory"); |
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#else |
#else |
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asm volatile("" : : : "memory"); |
asm volatile("" : : : "memory"); |
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#endif |
#endif |
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asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
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#elif defined(__x86_64__) |
#elif defined(__x86_64__) |
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asm volatile("mfence" : : : "memory"); |
asm volatile("mfence" : : : "memory"); |
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#elif defined(__ARM_ARCH_7A__) |
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asm volatile("dmb" : : : "memory"); |
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#else |
#else |
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asm volatile("" : : : "memory"); |
asm volatile("" : : : "memory"); |
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#endif |
#endif |
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case memory_order_seq_cst: |
case memory_order_seq_cst: |
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case memory_order_release: // (invalid) |
case memory_order_release: // (invalid) |
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#ifdef _ARCH_PPC |
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atomic_thread_fence(memory_order_seq_cst); |
atomic_thread_fence(memory_order_seq_cst); |
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#endif |
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// fall-through |
// fall-through |
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case memory_order_acquire: |
case memory_order_acquire: |
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: "memory", "cr0"); |
: "memory", "cr0"); |
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#else |
#else |
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m = f; |
m = f; |
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asm volatile("" : : : "memory"); |
atomic_thread_fence(memory_order_acquire); |
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#endif |
#endif |
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break; |
break; |
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} |
} |
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case memory_order_seq_cst: |
case memory_order_seq_cst: |
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case memory_order_acquire: // (invalid) |
case memory_order_acquire: // (invalid) |
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#ifdef _ARCH_PPC |
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atomic_thread_fence(memory_order_seq_cst); |
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f = m; |
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#else |
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atomic_thread_fence(memory_order_release); |
atomic_thread_fence(memory_order_release); |
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f = m; |
f = m; |
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atomic_thread_fence(memory_order_seq_cst); |
atomic_thread_fence(memory_order_seq_cst); |
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#endif |
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break; |
break; |
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} |
} |
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} |
} |