/[svn]/linuxsampler/trunk/src/common/lsatomic.h
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Contents of /linuxsampler/trunk/src/common/lsatomic.h

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Revision 1794 - (show annotations) (download) (as text)
Sun Nov 30 09:10:07 2008 UTC (15 years, 4 months ago) by persson
File MIME type: text/x-c++hdr
File size: 4604 byte(s)
* fixed crash on x86_64, introduced in 2008-11-02 commit (#108)
* fixed configure so it detects x86_64 (#107)

1 /***************************************************************************
2 * *
3 * Copyright (C) 2008 Andreas Persson *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the Free Software *
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *
18 * MA 02110-1301 USA *
19 ***************************************************************************/
20
21 #ifndef LSATOMIC_H
22 #define LSATOMIC_H
23
24 /*
25 * Implementation of a small subset of the C++0x atomic operations
26 * (cstdatomic).
27 *
28 * The supported operations are:
29 *
30 * - fences (acquire, release and full)
31 *
32 * - load and store of atomic<int> with relaxed, acquire/release or
33 * seq_cst memory ordering
34 *
35 * The supported architectures are x86 and powerpc.
36 */
37 namespace LinuxSampler {
38 enum memory_order {
39 memory_order_relaxed, memory_order_acquire,
40 memory_order_release, memory_order_seq_cst
41 };
42
43 inline void atomic_thread_fence(memory_order order) {
44 switch (order) {
45 case memory_order_relaxed:
46 break;
47
48 case memory_order_acquire:
49 case memory_order_release:
50 #ifdef _ARCH_PPC64
51 asm volatile("lwsync" : : : "memory");
52 #elif defined(_ARCH_PPC)
53 asm volatile("sync" : : : "memory");
54 #else
55 asm volatile("" : : : "memory");
56 #endif
57 break;
58
59 case memory_order_seq_cst:
60 #ifdef _ARCH_PPC
61 asm volatile("sync" : : : "memory");
62 #elif defined(__i386__)
63 asm volatile("lock; addl $0,0(%%esp)" : : : "memory");
64 #elif defined(__x86_64__)
65 asm volatile("mfence" : : : "memory");
66 #else
67 asm volatile("" : : : "memory");
68 #endif
69 break;
70 }
71 }
72
73 template<typename T> class atomic {
74 public:
75 atomic() { }
76 atomic(T m) : f(m) { }
77 T load(memory_order order = memory_order_seq_cst) const volatile {
78 T m;
79 switch (order) {
80 case memory_order_relaxed:
81 m = f;
82 break;
83
84 case memory_order_seq_cst:
85 case memory_order_release: // (invalid)
86 atomic_thread_fence(memory_order_seq_cst);
87 // fall-through
88
89 case memory_order_acquire:
90 #ifdef _ARCH_PPC
91 // PPC load-acquire: artificial dependency + isync
92 asm volatile(
93 #ifdef _ARCH_PPC64
94 "ld %0,%1\n\t"
95 #else
96 "lwz%U1%X1 %0,%1\n\t"
97 #endif
98 "cmpw %0,%0\n\t"
99 "bne- 1f\n\t"
100 "1: isync"
101 : "=r" (m)
102 : "m" (f)
103 : "memory", "cc");
104 #else
105 m = f;
106 asm volatile("" : : : "memory");
107 #endif
108 break;
109 }
110 return m;
111 }
112
113 void store(T m, memory_order order = memory_order_seq_cst) volatile {
114 switch (order) {
115 case memory_order_relaxed:
116 f = m;
117 break;
118
119 case memory_order_release:
120 atomic_thread_fence(memory_order_release);
121 f = m;
122 asm volatile("" : : : "memory");
123 break;
124
125 case memory_order_seq_cst:
126 case memory_order_acquire: // (invalid)
127 atomic_thread_fence(memory_order_release);
128 f = m;
129 atomic_thread_fence(memory_order_seq_cst);
130 break;
131 }
132 }
133 private:
134 T f;
135 };
136 }
137 #endif

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