/[svn]/linuxsampler/trunk/src/common/lsatomic.h
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Contents of /linuxsampler/trunk/src/common/lsatomic.h

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Revision 1792 - (show annotations) (download) (as text)
Sun Nov 16 19:19:26 2008 UTC (12 years, 2 months ago) by persson
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* fixes for building on OS X

1 /***************************************************************************
2 * *
3 * Copyright (C) 2008 Andreas Persson *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the Free Software *
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *
18 * MA 02110-1301 USA *
19 ***************************************************************************/
20
21 #ifndef LSATOMIC_H
22 #define LSATOMIC_H
23
24 /*
25 * Implementation of a small subset of the C++0x atomic operations
26 * (cstdatomic).
27 *
28 * The supported operations are:
29 *
30 * - fences (acquire, release and full)
31 *
32 * - load and store of atomic<int> with relaxed, acquire/release or
33 * seq_cst memory ordering
34 *
35 * The supported architectures are x86 and powerpc.
36 */
37 namespace LinuxSampler {
38 enum memory_order {
39 memory_order_relaxed, memory_order_acquire,
40 memory_order_release, memory_order_seq_cst
41 };
42
43 inline void atomic_thread_fence(memory_order order) {
44 switch (order) {
45 case memory_order_relaxed:
46 break;
47
48 case memory_order_acquire:
49 case memory_order_release:
50 #ifdef _ARCH_PPC64
51 asm volatile("lwsync" : : : "memory");
52 #elif defined(_ARCH_PPC)
53 asm volatile("sync" : : : "memory");
54 #else
55 asm volatile("" : : : "memory");
56 #endif
57 break;
58
59 case memory_order_seq_cst:
60 #ifdef _ARCH_PPC
61 asm volatile("sync" : : : "memory");
62 #elif defined(__i386__) || defined(__x86_64__)
63 asm volatile("lock; addl $0,0(%%esp)" : : : "memory");
64 #else
65 asm volatile("" : : : "memory");
66 #endif
67 break;
68 }
69 }
70
71 template<typename T> class atomic {
72 public:
73 atomic() { }
74 atomic(T m) : f(m) { }
75 T load(memory_order order = memory_order_seq_cst) const volatile {
76 T m;
77 switch (order) {
78 case memory_order_relaxed:
79 m = f;
80 break;
81
82 case memory_order_seq_cst:
83 case memory_order_release: // (invalid)
84 atomic_thread_fence(memory_order_seq_cst);
85 // fall-through
86
87 case memory_order_acquire:
88 #ifdef _ARCH_PPC
89 // PPC load-acquire: artificial dependency + isync
90 asm volatile(
91 #ifdef _ARCH_PPC64
92 "ld %0,%1\n\t"
93 #else
94 "lwz%U1%X1 %0,%1\n\t"
95 #endif
96 "cmpw %0,%0\n\t"
97 "bne- 1f\n\t"
98 "1: isync"
99 : "=r" (m)
100 : "m" (f)
101 : "memory", "cc");
102 #else
103 m = f;
104 asm volatile("" : : : "memory");
105 #endif
106 break;
107 }
108 return m;
109 }
110
111 void store(T m, memory_order order = memory_order_seq_cst) volatile {
112 switch (order) {
113 case memory_order_relaxed:
114 f = m;
115 break;
116
117 case memory_order_release:
118 atomic_thread_fence(memory_order_release);
119 f = m;
120 asm volatile("" : : : "memory");
121 break;
122
123 case memory_order_seq_cst:
124 case memory_order_acquire: // (invalid)
125 atomic_thread_fence(memory_order_release);
126 f = m;
127 atomic_thread_fence(memory_order_seq_cst);
128 break;
129 }
130 }
131 private:
132 T f;
133 };
134 }
135 #endif

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